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C HAPTER 1: D ESIGN F LOW
D ESIGN M ETHODOLOGIES AND P LANNING
f
For Information About
Using Quartus II incremental
compilation
Refer To
Quartus II Incremental Compilation for
Hierarchical & Team-Based Design chapter
in volume 1 of the Quartus II Handbook
“About Incremental Compilation” in
Quartus II Help
“Module 7: Incremental Compilation” in the
Quartus II Interactive Tutorial
Using LogicLock Regions
A LogicLock region is defined by its size and location on the device. You can
specify the size and location of a region, or direct the Quartus II software to
create them automatically.
With the LogicLock design flow, you can define a hierarchy for a group of
regions by declaring parent and child regions. The Quartus II software
places child regions completely within the boundaries of a parent region.
You can lock a child module relative to its parent region without
constraining the parent region to a locked location on the device.
You can create and modify LogicLock regions by using the Chip Planner, the
LogicLock Regions Window command on the Assignments menu, the
Hierarchy tab of the Project Navigator, or by using Tcl scripts. All LogicLock
attributes and constraint information (clock settings, pin assignments, and
relative placement information) are stored in the Quartus II Settings File for
the project.
You can also use the LogicLock Regions Properties dialog box to edit
existing LogicLock regions, view information about the LogicLock regions
in the design, and determine which regions contain illegal assignments.
In addition, you can add path-based assignments (based on source and
destination nodes), wildcard assignments, and Fitter priority for path-based
and wildcard assignments to LogicLock regions. Setting the priority allows
you to specify the order in which the Quartus II software resolves conflicting
path-based and wildcard assignments.
A LTERA C ORPORATION
I NTRODUCTION TO THE Q UARTUS II S OFTWARE
■
15
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相关PDF资料
SW-QUARTUS-SE-FLT SUBSCRIPTION FLOATALL REPL
SW006012 C COMPILER FOR DSPIC30F FAMILY
SW006013 C COMPILER MPLAB FOR DSPIC DSC
SW006015 C COMPILER MPLAB C32
SW300003-EVAL LIBRARY SOFT MODEM-EVAL ONLY
SW300010-EVAL SPEECH RECOG LIBRARY-EVAL ONLY
SW300040-EVAL LIBRARY NOISE SUPPR-EVAL ONLY
SW300060-EVAL LIBRARY ACOUSTIC ECHO-EVAL ONLY
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SW-QUARTUS-SE-FLT 功能描述:开发软件 FLOATING LICENSE FOR QUARTUS II RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
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SWR-10-12 制造商:Raxxess 功能描述:Wall Mount 10RU Hinged Rack with 12" Usable Depth
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